Khanh N. Dang, Ph.D.

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Picture of me with long hair and beard at IEEE MCSoC 2019 :P


  • (Oct. 2019) Our paper titled “TSV-OCT: A scalable online multiple TSV defects localization for 3D-ICs” is accepted for IEEE Trans. on VLSI systems!

  • (Oct. 2019) Our paper is accepted for IEEE APCCAS 2019 in Bangkok, Thailand on Nov. 11-14, 2019!

  • (Jul. 2019) Our paper is accepted for IEEE MCSoC 2019 in NTU, Singapore on Oct. 1-4, 2019!

  • (May. 2019) Our new VNU JCSCE journal paper has been published here! The paper proposed a method to adapt coding techniques with several error rates and inform the system whether it cannot correct the current faulty rate.

  • (May. 2019) I will be an invited external lecturer for SYC04 - Advanced Computer Organization class in May 2019. The lecture is about designing and implementing 3D-Network-on-Chip on ASIC.

  • (Apr. 2019) Our paper is accepted for ISVLSI 2019 in Florida, on July 15-17, 2019! The paper is about on-line and non-block testing for Through-Silicon-Vias in 3D-ICs. The paper could be seen here.

  • (Dec. 2018) I will be a visiting researcher at The University of Aizu (May 2019 - Sep. 2019) to work on designing Spiking Neural Network on hardware (ASIC/FPGA). The STDP on-line learning algorithm is also targeted for implementation.


Room 2.1, E4, Vietnam National University, Hanoi
144 Xuan Thuy Rd., Hanoi, Vietnam
Email: khanh.n.dang ατ